Currently, the scientific group has started the second project activity "Decomposition: Development of Methods and Algorithms". The scientific literature in the field of decomposition is selected and the existing decomposition algorithms are analysed.

In the first activity “Implementation model exhibition” it was found out that the current approach to decomposition is intended for circuits with simple logic elements (AND-NOT, OR-NOT), to avoid competition, double-track representation is used (variable and its inversion is represented by two separate signals) . As a result, technical costs are very high. CMOS logic reduces complexity. Another approach is based on the use of threshold functions (Zero Convention Logic -NCL). NCL is built using 27 library elements that can implement any function with four or fewer inputs. Since a double-track representation is provided, single-track functions with more than two inputs cannot be used in the NCL environment, the feasibility of the functions depends on the number of literals in the double-track representation.

Features of the reconfigurable environment architecture function:

1) functional blocks (browser tables) that are able to implement any function with the given browser table inputs;

2) the delay from each input to output is the same;

3) wires between browsers with unknown and sometimes large delays;

4) internal feedback.

Therefore, the methods previously used in the design based on simple elements should be reviewed, although each individual browser table does not contain competition (browser table delays balanced), remains an important problem in the implementation of the overall scheme without competition. Due to the large delays in the wires, a model with unlimited delays is provided, i. delay insensitive model.

The decomposition must ensure the division of the scheme into a network of sub-schemes in such a way that each sub-scheme can be implemented using browser tables. In addition, the decomposition must be produced in a sub-network without competition. Possible problems:

1) decomposition cannot produce a network without competition;

2) the relevant network can be produced but there is no possibility to connect modules (lack of wires in the environment).

In this case, the circuit fragment must be re-decomposed to allow implementation. Problems will be addressed and alternative

 re-decomposition methods will be developed. In the subfunctions obtained by decomposition, the main criterion is the number of literals (which is equivalent to the number of input signals).

The project will offer an implementation model that corresponds to the architecture of the reconfigurable environment, methods and tools: decomposition, function minimization, signalling, deployment and routing, and evaluation of the efficiency of the design procedure.

The research will be implemented in the ERDF Operational Program “Growth and Employment” 1.1.1. Specific support objective “To increase the research and innovation capacity of Latvian scientific institutions and the ability to attract external funding by investing in human resources and infrastructure” 1.1.1.1. within the framework of the measure “Practical Orientation Research”. The project will be implemented for 36 months, until February 29, 2020. Project “Asynchronous Logic Circuits: Methods and Software Tools for Designing in a Configurable Environment”, No. 1.1.1.1/16/A/234, the funding is EUR 287 891.90.

For more detailed information: : infovirac@venta.lv